Curated publication records
Publications
Technical publications, papers, and credited contributions.
A focused publication catalog for Bertrand Blanc: authored and co-authored technical material first, with clearly labelled credited contributions where the legacy archive names the contribution but not authorship.
Author or co-author records
Clearly labelled contributions
Publication Library
Selected technical record
Each card presents the publication context, authorship, and available files clearly. Unavailable references stay visibly disabled instead of pretending to be clickable.
Industry posterAuthor metadata
A Next Generation IP and SoC Development Platform
Design Automation Conference DAC'12, User Track Poster Session 6U.2
A poster on a next-generation IP/SoC design environment for seamless design, verification, and integration methodology, automating the delivery and assembly of production-ready IP components for Altera integration teams.
LinkedIn reference: Listed on LinkedIn
Industry presentationAuthor
In the Context of IP-XACT: DAC'08 Market Trends
DAC'08 exhibition outcome, Anaheim, California
A round-table support presentation on IP-XACT, W3C, and Eclipse market trends, prepared after the DAC'08 exhibition and retained in the 3BC archive.
Conference presentationAcknowledged contributor
Register Management of a Complex Multi-Processor Based SoC
ARM Developers' Conference, Santa Clara, California
A presentation on single-source software/hardware interface modeling, coherence checking, collaboration, and automation for complex multiprocessor SoC register-management flows.
Symposium publicationLinkedIn-listed publication
Common Platform for SoC Integration and Verification
Texas Instruments Symposium on IC Design Verification, Dallas, USA
A LinkedIn-listed publication connected to SoC integration and verification methodology. It is kept as a public-profile record because no local PDF artifact has been identified in the active cache.
LinkedIn reference: Listed on LinkedIn
No public file linked
White paperCo-author
Endianness or Where is Byte 0?
3B Consultancy / Texas Instruments register-methodology material
A practical white paper on byte ordering, register layout, and the concrete ambiguity created when hardware and software teams do not share a precise convention for byte zero.
LinkedIn reference: Listed on LinkedIn
Proceedings contributionAdditional referee
Correct Hardware Design and Verification Methods
CHARME'05, Saarbrucken, Germany, Springer proceedings
A proceedings credit for reviewing contributions submitted to CHARME 2005, recorded in the personal testimonials archive as an additional referee contribution.
No public file linked
Conference paperCo-author
Multiclock Design and Synthesis with Esterel
7th SAME'04 Forum on Microelectronics, Sophia-Antipolis
A conference paper on multiclock design and synthesis using Esterel, produced from Texas Instruments and Esterel Technologies work and recorded in the legacy material as an awarded SAME'04 paper.
LinkedIn reference: Listed on LinkedIn
Technical paperAuthor / principal contributor
Register Description: Methodology for Reusable Register Capture
Texas Instruments / Esterel Technologies technical work
A technical paper connected to the Register Description work: a language and flow for describing registers, components, and subsystems once, then reusing that source across architecture, verification, validation, and technical-reference material.
Workshop presentationAuthor
Translating Pure Esterel v5 into Behavioral VHDL
9th International Open Workshop on Synchronous Reactive Languages, SYNCHRON'02
A research presentation from INRIA work on translating structured Esterel programs into behavioral VHDL, covering interoperability, semantic relationships between Esterel and VHDL, workflow, control-flow dispatching, concurrency, causality, and absence handling.
Technical reportAuthor
DEA Report: Translating Esterel Toward Behavioral VHDL
INRIA Sophia-Antipolis, TICK project
A research report connected to the INRIA internship on translating structured Esterel programs into behavioral VHDL while preserving behavioral structure and simulation semantics.
Technical documentationAuthor
makehdltb Manual
Esterel Technologies hardware test-bench generation work
A technical manual for a hardware-description-language test-bench generator taking an Esterel interface and scenario file, then generating VHDL, Verilog, C, or C++ test-bench output.
Technical reportAuthor / project report
Real-Time Experiment Control Language and Simulator
CNRS electronics and computer-science laboratory internship
A French technical report connected to CNRS work defining specifications and implementing a language for real-time experiment-control schemes, including behavioral modeling and simulation support.